JESD204C / JESD204B Interface
VITA 57.1 FMC 

• Wide Dynamic Range
  
• High Channel Density
  
• Ideal for SWaP-C Sensi􀀁ve Application
• Designed for Xilinx UltraScale and UltraScale+ FPGA Carrier Boards
  
• Built-in Clock Jitter Cleaner 
  
• Configurable digital up/down conversion (DDC/DUC) 

Download Datasheet

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The DEG ADF-QMX44 FMC leverages the Analog Devices AD9081 MxFE (Mixed Signal Front End) transceiver technology. This highly  integrated device, includes a quad 16-bit, 12 Gsps sample rate radio frequency (RF) digital-to-analog converter (DAC) and a quad 12-bit, 4 Gsps rate RF analog-to-digital converter (ADC). The ADF-QMx44 features an 8-lane, 24.75 Gbps JESD204C transceiver port, an on-chip clock multiplier, digital signal processing capability and supports four transmitter channels and four receiver channels.

The  ADF-QMX44 is a VITA 57.1-2019 compliant FPGA Mezzanine Card (FMC) that offers industry-wide platform compatibility with Xilinx UltraScale and UltraScale+ FPGA carrier boards, including DEG’s performance-leading, PCI Express and 3U Open VPX carrier products. 

ADCLink

Implementation and control of the ADF-QMX44 is accomplished with Delphi’s ADCLink. The capabilities of ADCLink include clock phase adjustment, onboard/external reference clock control, trigger input, thresholds and ADC and DAC mode control.

Flexible & Cost-Effective Solution

By coupling this core architecture with the compact and flexible FMC form factor, DEG has enabled customers to rapidly and cost-effectively build compact and rugged systems of high-speed digitization on a single high-performance FPGA carrier board. The front panel of the ADF-QMX44 provides ten coaxial connections that serve as inputs for a trigger and clock, four analog inputs and four analog outputs.