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DSP32130S
Rad Hard DSP Module With FPGAs
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Delphi Engineering Group's
DSP32130S is a reconfigurable computing platform designed to tackle
demanding DSP tasks such as image
processing, radar, data compression, and signal intelligence.
Two C6701 floating point DSPs allow real-time processing
of high bandwidth data streams.
Designed to operate under challenging space conditions, the
DSP32130S is with Single Event Upset (SEU), Single Event
Latch-Up (SEL), and Single Event Transient (SET) hardening.
Triple Mode Redundancy (TMR) is utilized for memory protection.
The DSP32130S offers high performance and wide flexibility
with two Texas Instruments' TMS320C6701. The C6701 DSP
has ability to execute 8 instructions per clock cycle,
up to 1864 MIPS peak processing power is on hand with each processor.
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General
• TI Space Grade TMS320C6701 DSP
Rad Hard to 100 krads (Si)
512k-Bit Program Memory
2000 MFLOPS
512k-Bit Data Memory (2 Blocks)
6 ns at 167 MHz Cycle Time
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Two FPGAs
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TMR (Triple Modular Redundancy) Memory
Protection
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SEU (Single Event Upset) Immune
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SEL (Single Event Latch-Up) Immune
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Megabyte Flash
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192 or 384 MB SDRAM Buffer (128 or 256
MSample Storage Capacity)
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VITA-35 Compliant Pn4 Interface With 32
LVDS Pairs
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VxWorks, Linux, Windows Software Drivers
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32/64-bit Up to 100 MHz, 3.3V, PCI 2.2 or
PCI-X Compliant Bus
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Onboard DMA Engine
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1553, Spacewire, RS485, cPCI
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| Applications |
• RADAR
• LADAR/LiDAR
• Beamforming
• SATCOM
• Data Analysis Systems
• Preprocessing Systems
• Direct RF Down-Conversion
• Multi-Carrier Power Amplifiers
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